Memory speed and memory capacity continue to increase to meet the demands of system applications. Some of these system applications include mobile electronic systems that have limited space and limited power resources. In mobile applications, such as cellular telephones and personal digital assistants (PDAs), memory cell density and power consumption are issues for future generations.
To address these issues, the industry is developing random access memories (RAMs) for mobile applications. One type of RAM, referred to as CellularRAM, is a high performance and low power memory designed to meet the growing memory density and bandwidth demands of future designs. CellularRAM is a pseudo static RAM (PSRAM) that offers a lower cost per bit ratio than current solutions. Also, CellularRAM offers static random access memory (SRAM) pin and function compatibility, external refresh-free operation, and a low power design. CellularRAM devices are drop-in replacements for most asynchronous low power SRAMs currently used in mobile applications, such as cellular telephones.
Typically, a PSRAM is based on a dynamic random access memory (DRAM) that provides significant advantages in density and speed over traditional SRAM. The DRAM can include one transistor and one capacitor memory cells that are arranged in one or more arrays of memory cells, which are arranged in memory banks. To read and write memory cells, each DRAM includes one or more row decoders, one or more column decoders, and sense amplifiers. The sense amplifiers can be differential sense amplifiers, wherein each sense amplifier receives one bit line at each of two differential inputs.
To read or write memory cells, the DRAM receives a row address, a column address, and control signals. A row decoder receives the row address to select a row of memory cells and a column decoder receives the column address to select one or more columns of memory cells. Each memory cell at the intersection of a selected row and a selected column provides a data bit to a sense amplifier.
At each sense amplifier that receives data, one of the bit lines receives the data bit from a selected memory cell and the other bit line is used as a reference. To read the data bit, the sense amplifier amplifies the difference between the data bit value and the reference value and provides a sensed output value to an output driver. To write a data bit into a selected memory cell, input drivers overdrive the sense amplifier. One input driver overdrives a data bit value onto the bit line that is connected to the selected memory cell and another input driver overdrives the inverse of the data bit value onto the reference bit line.
In some situations, a write command is issued to write selected memory cells, but some of the selected memory cells have been masked or columns of memory cells have been replaced with redundant columns of memory cells. Typically, to block the write command, a column connected to a masked or replaced memory cell is activated to access the memory cell as in normal writes and a high voltage level is driven onto each of the differential inputs of the connected sense amplifier. The sense amplifier does not detect a voltage difference in the data lines and therefore does not drive the bit lines, which prevents writing the accessed memory cell. However, transistors in the drivers may be mismatched. One driver may supply a higher voltage than the other driver causing the sense amplifier to be biased in one direction to leak charge away from a masked memory cell. Leaking charge away from a masked memory cell can cause data retention problems. Also, drivers and sense amplifiers use current when driven and, in mobile applications, power is a limited resource.
For these and other reasons there is a need for the present invention.